1. Field of the Invention
The present invention generally relates to an ESD clamp circuit, and more particularly, to an ESD clamp circuit that can avoid the problem of signal loss caused by the leakage current.
2. Description of Related Art
Nowadays, the manufacture process technology of complementary metal-oxide semiconductor (CMOS) device is developed to nano-meter scale. In order to combine with other CMOS circuit to achieve a design of system-on-a-chip (SOC), a radio frequency (RF) circuit designed by the manufacture process of SiGe would be substituted by the manufacture process of CMOS. In order to discharge ESD current effectively, ESD protection elements are placed at an input/output (I/O) ports and between power-rails to protect the core circuits from damage.
In order to output high power in the MOS power amplifier design, NMOS with big size served as output stage device is required. Moreover, considering the current density, the inductor placed between VDD power line and the drain of the big size NMOS would occupy a large IC layout area. Therefore, to integrate this large inductor into the same IC is inadvisable. For this reason, the inductor may be disposed off chip, and the rest of the principal power amplifier circuit is designed on the same chip, shown as FIG. 1.
FIG. 1 is a schematic diagram illustrating a conventional power amplifier. Referring to FIG. 1, to achieve ESD protection of the IC completely, a power-rail ESD clamp circuit 110 have to disposed between a output terminal Vout1 of the power amplifier 100 and a ground voltage VSS to discharge ESD current, so as to prevent inner elements damaged. In addition, if design of conventional power-rail ESD protection is used at normal operation, a problem of signal loss is generated by the power amplifier 100 caused by the leakage current of power-rail ESD clamp circuit 110.
FIG. 2 is a schematic diagram illustrating the power amplifier of FIG. 1 and an additional ESD protection circuit thereof. Referring to FIG. 2, while a power amplifier 200 operates in normal, an output terminal of the power amplifier 200 has a voltage signal, which has a high frequency and a voltage level higher than a power VDD. The frequency of the voltage signal is so high that the frequency of a voltage signal at node A between a resistor and a capacitor of an ESD clamp circuit 210 can not follow the frequency of the voltage signal. Therefore, the voltage level at node A is still equal to the voltage level the power VDD, and oscillates with the voltage signal with small amplitude. A transistor M2 in an inverter which composed of the transistor M2 and a transistor M3 turns on to charge the gate terminal of a transistor M1 according to a voltage difference between the voltage level at node A and the voltage signal having a high frequency and a voltage level at node B. Therefore, a voltage at node C is higher than a threshold voltage of the transistor M1, so that the transistor M1 is turned on to form a leakage path under the power amplifier 200 operates in normal. An output signal of the power amplifier 200 has distortion caused by the leakage current flowing through the leakage path.
FIG. 3 is a schematic diagram of illustrating a voltage wave of ESD clamp circuit of FIG. 2. Referring to FIG. 3, a curve 301 is a voltage wave at node B of FIG. 2, a curve 302 is a voltage wave at node A of FIG. 2, a curve 303 is a voltage wave at node C of FIG. 2, and a dotted line 304 is the threshold voltage of the transistor M1. Referring to the curve 303 and the dotted line 304, while the voltage at node C is higher than the threshold voltage of the transistor M1, so that the transistor M1 is turned on to form a leakage path under the power amplifier 200 operates in normal. An output signal of the power amplifier 200 has distortion caused by the leakage current flowing through the leakage path.
FIG. 4 is another schematic diagram illustrating the power amplifier of FIG. 1 and an additional ESD protection circuit thereof. Referring to FIG. 4, a signal outputted from the output terminal Vout3 of a power amplifier 400 is coupled to node D through a capacitor. While an output voltage of the amplifier 400 is so high that voltage at node D is higher than threshold voltage of the transistor M4, and the transistor M4 is turned on to form a leakage path. The output signal of the power amplifier 400 has distortion caused by the leakage current flowing through the leakage path.
FIG. 5 is a schematic diagram illustrating a voltage wave of ESD clamp circuit of FIG. 4. Referring to FIG. 5, a curve 501 is a voltage wave at node E of FIG. 4, a curve 502 is a voltage wave at node D of FIG. 4, and a dotted line 503 is the threshold voltage of the transistor M4. Referring to the curve 502 and the dotted line 503, while the voltage at node D is higher than the threshold voltage of the transistor M4, so that the transistor M4 is turned on to form a leakage path. An output signal of the power amplifier 400 has distortion caused by the leakage current flowing through the leakage path.
FIG. 6 is a schematic diagram illustrating a radio frequency power amplifier circuit of U.S. Pat. No. 7,280,330. Referring to FIG. 6, in an ESD clamp circuit, a capacitor resistor (CR) structure is serving as an ESD detection circuit. While an ESD event occurred, a diode D1 is biased with a part of voltage between PAout and VSS, which is an ESD path, and thus transistors 620 and 630 are turned on due to high voltage of the ESD, which is coupled to the gates of transistors 620 and 630 through a transistor-based capacitor 610. While the ESD passes from VSS to PAOUT, the diode D2 between PAOUT and VSS in the ESD clamp circuit is forward turned on to discharge an ESD current. While a radio frequency power amplifier operates in normal mode, the diode D1 achieves a clamp function, so that a voltage signal outputted from PAOUT decayed by the diode D1 is not enough to turn on an output ESD cell 650. Thereby, in the normal mode, the output ESD cell 650 may not influence normal work of the circuit.